Large Scale Integration (LSI) construction of complex digital logic interconnected to provide a complete system on a single integrated circuit chip has greatly reduced space limitations on the chip by allowing for higher density of the semiconductor devices. Since only a relatively small number of different logical functions are required to provide a variety of complex subsystems, identical sections of the integrated circuit containing a plurality of each of several basic logic circuits can be fabricated into different subsystems as determined by the circuit interconnections. The semiconductor devices are formed by conventional procedures and may be arranged in an array of standard cells. The devices of each cell may be interconnected to form one or more different types of logic circuits, and the logic circuits may be interconnected to form the desired system.
In the manufacture of digital logic systems in this manner, standard cells are typically provided which may be customized by forming metal interconnections by conventional means to interconnect the devices of selected cells to provide the basic logic circuit for the system. High density packing of logic arrays offer both a large reduction in system component count and power dissipation. However, previously known logic circuits and arrays have drawbacks in that the metallization used for interconnection of the semiconductor devices and for supplying the power thereto limits the complexity of the integrated circuit due to the space required by the metal. The large plurality of semiconductor devices in the logic circuit have created a need for a complex weaving of the current carrying paths within the metallization layers that overlie the devices for connecting one device to another.
Furthermore, for custom circuits, the time typically required to complete the manufacture of the chip after circuit design (metallization, packaging, etc.) is several weeks.
Thus, what is needed is a logic circuit wherein the metallization required for interconnection of semiconductor devices is reduced and wherein the manufacture of the chip may be completed prior to circuit design.